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CompuLab Ltd. IPC2 – Hardware Specification Page 51 of 83

5.1.2 Mini PCI Express* Edge Connector

Table 28 – mini PCI Express edge connector pinout

mini PCI Express edge connector

Pin #

Pin Name

Signal Description

Pin #

Pin Name

Signal Description

1

WAKE#

Open drain, active low signal driven low by a

mini PCIe card to reactivate the PCIe link

2

3.3V

3.3V power rail

3

COEX1/Reserved

Reserved for future wireless coexistence

control interface between radios (if needed)

4

GND

Ground connection

5

COEX2/Reserved

6

1.5V

1.5V power rail

7

CLKREQ#

Clock request - open drain, active low driven

by mini PCIe card to request PCIe reference

clock

8

UIM_PWR/Reserved

The UIM signals are defined on the system

connector to provide the interface between

the removable User Identity Module (UIM)

Interface - an extension of SIM and WWAN.

9

GND

Ground connection

10

UIM_DATA/Reserved

11

REFCLK-

PCI Express differential reference clock (100

MHz)

12

UIM_CLK/Reserved

13

REFCLK+

14

UIM_RESET/Reserved

15

GND

Ground connection

16

UIM_VPP/Reserved

Mechanical Notch Key

17

Reserved/UIM_C8

Reserved

18

GND

Ground connection

19

Reserved/UIM_C4

Reserved

20

W_DISABLE#

Active low signal when asserted by the

system disable radio operation. Reserved for

future use.

21

GND

Ground connection

22

PERST#

Asserted when power is switched off and also

can be used by the system to force HW reset

23

PERn0

PCI Express differential receive pair

24

3.3V

3.3V power rail

25

PERp0

26

GND

Ground connection

27

GND

Ground connection

28

1.5V

1.5V power rail

29

GND

Ground connection

30

SMB_CLK

Not Connected

31

PETn0

PCI Express differential transmit pair

32

SMB_DATA

33

PETp0

34

GND

Ground connection

35

GND

Ground connection

36

USB_D-

USB Host Interface

37

GND

Ground connection

38

USB_D+

39

3.3V

Not Connected

40

GND

Ground connection

41

3.3V

Not Connected

42

LED_WWAN#

Not Connected

43

GND

Ground connection

44

LED_WLAN#

Active low output signals are provided to

allow status indications to users via system

provided LEDs

45

CLink_CLK

Clock signal on specific Intel AMT interface

46

LED_WPAN#

Not Connected

47

CLink_DATA

Data signal on specific Intel AMT interface

48

1.5V

1.5V power rail

49

CLink_RST

Reset signal on specific Intel AMT interface

50

GND

Ground connection

51

Reserved

Not Connected

52

3.3V

3.3V power rail

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 82 83

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