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6.5.2 Connectors Pinout
The tables below provide complete pinout of extension connector EXT1 and signals mapping.
Table 39 – EXT1 connector HOST side pinout
EXT-1 connector HOST side
Pin #
Signal Name
Signal Description
Pin #
Signal Name
Signal Description
A1
GND
Ground connection
B1
GND
Ground connection
A2
SATA2_TX+
SATA2.0 differential transmit pair 2; Host
signal shared with mini PCIe (MUX channel
B)
B2
CLK1_PCIE+
Host PCIe CLK output differential pair
- 100MHz
A3
SATA2_TX-
B3
CLK1_PCIE-
A4
CIR_RX/SIO_GPIO15
SuperIO GPO, PU-10k
B4
SATA0_LED
SATA activity LED indicator
A5
SATA2_RX+
SATA2.0 differential receive pair 2; Host
signal shared with mini PCIe (MUX channel
B)
B5
CLK_PCIE_PLX2+
Host PCIe CLK output differential pair
- 100MHz
A6
SATA2_RX-
B6
CLK_PCIE_PLX2-
A7
GND
Ground connection
B7
V5SBY
5V power domain
A8
SIO_GPIO16
SuperIO GPI, PU-weak
B8
SATA0_RX+
SATA3.0 differential receive pair 1
A9
SIO_GPIO30
SuperIO GPI, PD-100k
B9
SATA0_RX-
A10
SMB_ALRT#
SMBus Alert used to wake the system
B10
SLP_S4#
SLP_S4# - S4 state flag active low
output
A11
SIO_GPIO31
SuperIO GPI, PU-weak
B11
SATA0_TX+
SATA3.0 differential transmit pair 1
A12
SIO_GPIO37
SuperIO GPI, PU-weak
B12
SATA0_TX-
A13
V5SBY
5V power domain
B13
V5SBY
5V power domain
A14
SMB_CLK
SMBus host clock output. Connect to
SMBus slave
B14
NC
NC
A15
SMB_DAT
SMBus bidirectional data. Connect to
SMBus slave
B15
NC
NC
A16
HDA_RST#
High Definition Audio host reset
B16
SIO_GPIO35
SuperIO GPO, PU-10k
A17
HDA_SYNC
High Definition Audio host sync
B17
NC
NC
A18
HDA_BITCLK
High Definition Audio host bit clock out
24MHz
B18
NC
NC
A19
HDA_SDOUT
High Definition Audio serial host data out
B19
V5SBY
5V power domain
A20
SIO_GPIO36
SuperIO GPO, PD-10k
B20
Reserved
For internal use only
A21
HDA_SDIN1_EXT
High Definition Audio serial host data in0
B21
Reserved
For internal use only
A22
DEBUG3
Reserved debug signal
B22
LPC_SERIRQ
Serial Interrupt Request
A23
GND
Ground connection
B23
LPC_CLK
Single Ended 33MHz CLK host out to
PCI devices
A24
USB4_P
USB2.0 Host interface 0
B24
LPC_FRAME#
LPC interface frame signal
A25
USB4_N
B25
GND
Ground connection
A26
USB_OC0_1#
USB Overcurrent Indicator for SerDes 0/1
B26
Reserved
For internal use only
A27
USB5_P
USB2.0 Host interface 1
B27
Reserved
For internal use only
A28
USB5_N
B28
Reserved
For internal use only
A29
GND
Ground connection
B29
Reserved
For internal use only
A30
LPC_AD0
LPC bus multiplexed command, address
and data. Internal PU provided on LPC[3:0]
B30
Reserved
For internal use only
A31
LPC_AD1
B31
RESET#
Active Low Platform Reset driven by
the Host
A32
LPC_AD2
B32
CLK0_PCIE+
Host PCIe CLK output differential pair
- 100MHz
A33
LPC_AD3
B33
CLK0_PCIE-
- Hardware Specification 1
- Legal Notice 2
- Revision History 3
- Table of Contents 4
- Table of Figures 7
- Table of Tables 8
- 1 Introduction 10
- 1.3 Terms and Acronyms 11
- 2 System Overview 12
- 2.3 System Block Diagram 15
- 3 Platform 16
- 3.1.3.1 System States 18
- 3.2.1 Graphics Features 19
- 3.3 PCH (Chipset) 20
- 3.3.1.9 RTC 23
- 3.3.1.10 GPIO 23
- 3.4 Intel Management Engine 24
- 3.5 System Clocks 25
- 3.5.1 Functional Blocks 26
- 3.6 System Memory 28
- 3.7 Storage 32
- 3.7.1.1 HDD examples 33
- 3.7.1.2 mSATA SSD examples 37
- Table 25 – ACPI CMS2G-M SSD 38
- 4 Peripherals 39
- 4.2 Network 41
- 4.3 Wireless Networks 44
- 4.5 Audio 46
- 4.5.2 Audio Codec Features 46
- 4.6 Super-I/O Controller 49
- 5 Interfaces 50
- 5.2.1.1 HDMI Connector 54
- 5.3 USB Interface 60
- 5.4 RS232 Serial Interface 61
- 6 Miscellaneous Features 63
- B2B connector 65
- 6.5.1 Extension Connectors 66
- 6.5.2 Connectors Pinout 67
- USB3 Type-A 69
- Receptacle 69
- 6.5.3.5 Mechanics 70
- 6.5.3.5.1 PCB Assembly 70
- 6.5.3.5.2 Front Panel 70
- 7 Advanced Technologies 71
- 8 Power Management 73
- 9.4 Power Supply 75
- 10.1 Mechanical Drawings 76
- 10.1.1 Chassis 76
- 10.1.2 Single Board Computer 80
- 10.1.2.1 With FACE Module 80
- 10.2 Environmental 82
- 11 Resources 83
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