CompuLab IPC2 Manual de usuario Pagina 34

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CompuLab Ltd. FACE Modules HW Specifications Page 34 of 63
5.4.2 IDT ICS9DB102 1-to-2 Differential Clock Driver
IDT ICS9DB102 is two output clock buffer for PCIe Gen1 & Gen2 with HCSL current mode differential
outputs.
Device zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a
differential compliant input clock. It attenuates jitter on the input clock and has a selectable PLL Band
Width to maximize performance in systems with or without Spread-Spectrum clocking.
5.5 Mechanics
5.5.1 PCB Assembly
Figure 16 FM-XTDEU2/4 PCB Assembly Top
5.5.2 Front Panel
Figure 17 FM-XTDEU2/4 front panel drawing
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